The invention relates to electronic circuitry, and in particular to high-speed logic circuits and applications thereof.
With recent advances in the electronic industry, logic circuits of increased speeds are required to process high speed signals, for example 10 Gigabit/second and ultimately 40 Gigabit/second serial bit streams arising in fiber optic transmission systems.
At the same time, the logical complexity of the circuits is constantly increasing in order to meet ever increasing complexity and numerous requirements of processing, for example of SONET and fast Ethernet protocols.
To meet these requirements, silicon circuits using smaller geometry are being developed. Smaller geometry technology, such as xe2x80x9c0.18 micron technologyxe2x80x9d and below, provides the capability to design high density and complex CMOS circuits. The smaller geometry technology also provides a capability for higher speed circuitry.
Current Mode Logic (CML) circuitry has been developed by the industry to provide a high-speed logic circuit technology, which is compatible with CMOS circuitry, and allows the fabrication of both types of circuits in one device, or chip. Typically, the CMOS circuitry would provide the high-density complex logic processing part of the chip, while CML circuitry would be used in the high-speed serial interfaces that run at the serial bit rate and convert between the serial bit streams and the parallel bus signals processed by the CMOS circuitry. The speed of the serial interface may thus be many times higher than the speed of the CMOS circuitry.
In conventional synchronous logic design, a clock circuit drives the logic circuits including combinatorial logic functions (AND, OR, Mux, etc.) and storage elements (D-type flip-flops). In order to provide high-speed operation, it is necessary to control the current through each circuit to prevent saturation of the transistors (if bipolar technology is used) or triode region operation (if MOS technology is used).
A theoretical analysis of a basic CML circuitry can be found in the book xe2x80x9cAnalog Integrated Circuit Designxe2x80x9d by David Johns and Ken Martin, published by John Wiley and Sons, 1997, pp. 142. An exemplary implementation of the CML circuitry, based on tail current sources (bias stage) and differential current steering through transistor pairs, as described, e.g. in the U.S. Pat. No. 6,424,194 to Hairapetian U.S. Pat. No. 6,424,194 entitled xe2x80x9cCurrent-controlled CMOS logic familyxe2x80x9d issued Jul. 23, 2002, will be described with reference to FIGS. 1A to 1C below.
FIG. 1A shows one example of the prior art circuit arrangement 10 of a CML Logic Circuit 11 including a logic function circuit 12 coupled to a current source 14, and a CML Clock Buffer 15 including a driver circuit 16 coupled to a current source 18. The differential output 17 of the driver circuit 16 of the CML Clock Buffer 15 is coupled to a differential clock input 19 of the logic function circuit 12 of the CML Logic Circuit 11. The input 13 of the driver circuit 16 of the CML Clock Buffer 15 is connected to a clock source (not shown). The differential output 19a of the logic function circuit 12 of the CML Logic Circuit 11 is connected to other logic circuits (not shown). The logic function circuit 12 may include other differential inputs (illustrated by a straight unmarked line extending from the logic function circuit 12 on its left) connected to the outputs of other logic function circuits 12 (not shown).
The current source 14 of the CML Logic Circuit 11 provides a bias current to the logic function circuit 12, thus setting its operating point. Similarly, the current source 18 of the CML Clock Buffer 15 provides a bias current to the driver circuit 16, thus setting its operating point.
FIGS. 1B and 1C of the prior art show the details of the CML Logic Circuit 11 implemented in two technologies, namely the CML Logic Circuit 11 implemented by using a bipolar technology (CML Logic Circuit 20) and by using MOS technology (CML Logic Circuit 30) respectively. The detailed circuits 20 or 30 are representative of the combination of a typical logic function circuit 12 and current source 14 of the prior art.
The bipolar CML circuit 20 comprises transistors Q30, Q31n, Q31p, Q32n, Q32p, Q33n, and Q33p, as well as resistors R30, R31n, and R31p. The circuit is connected to power supply terminals Vcc, Vee, and a bias supply Vbias.
Differential data inputs in_n and in_p of the circuit are connected to an input data source (not shown), differential clock inputs ck_n and ck_p of the circuit are connected to a clock buffer (not shown), and differential data outputs out_n and out_p of the circuit are connected to a subsequent logic circuits (not shown). Differential inputs and outputs are pairs of terminals designated with the subscripts_n (negative) and_p (positive).
The power supply terminal Vcc is connected to a first lead 21 of the resistor R31n and a first lead 22 of the resistor R31p. Second leads of the resistors R31n and R31p (23 and 24) are respectively connected to the differential data outputs out_n and out_p. Also connected to the negative data output terminal out_n are the collectors of the transistors Q32n and Q32p as well as the base of the transistor Q33p. Further connected to the positive data output terminal out_p are the collectors of the transistors Q33n and Q33p as well as the base of the transistor Q32p. The differential data inputs in_n and in_p are connected to the bases of the transistors Q33n and Q32n respectively. The emitters of the transistors Q33n and Q32n are tied together and connected to the collector of the transistor Q31n. The emitters of the transistors Q33p and Q32p are tied together and connected to the collector of the transistor Q31p. The differential clock inputs ck_n and ck_p are connected to the bases of the transistors Q31n and Q31p respectively. The emitters of the transistors Q31n and Q31p are tied together and connected to the collector of the transistor Q30. The base of the transistor Q30 is connected to the bias supply Vbias, and the emitter of the transistor Q30 is connected to a first lead 25 of the resistor R30. A second lead of the resistor R30 (26) is connected to the power supply terminal Vee.
Transistors Q31n, Q31p, Q32n, Q32p, Q33n, and Q33p and resistors R31n and R31p form a conventional latch circuit, providing a latch function: the value of the signal at the differential inputs in_n and in_p are transferred to the differential outputs out_n and out_p upon activation of the differential clock inputs ck_n and ck_p. Upon de-activation of the differential clock inputs ck_n and ck_p, the latch retains the output value due to the cross-coupling between the outputs out_p and out_n, and the bases of the transistors Q32p and Q33p respectively.
The current source 14 of the bipolar CML circuit 20 includes the transistor Q30, the resistor R30, and the bias supply Vbias, to supply the bias current to the latch circuit (the logic function circuit 12).
In the CML circuits 20 of the prior art, the current source supplies a fixed current to the latch circuit, regardless of the operational state of the latch. This current flows through one of resistors R31n or R31p; through only one of the transistors Q32n, Q32p, Q33n, Q33p; and through one of the transistors Q31n and Q31p, depending on the state of the differential inputs in_n and in_p, and the differential clock inputs ck_n and ck_p.
The bias current is set, by the combination of the value of the bias supply Vbias and the resistor R30, to ensure that the voltage drop across resistors R31n or R31p (depending on the operational state of the latch) is high enough as a logic signal (voltage swing) at the circuit outputs out_n and out_p, but is not so high as to saturate the transistors.
The type of current source that is inserted between the power supply terminal Vee and the logic circuit proper is also referred to as a tail current source.
The MOS CML circuit 30 is analogous to the bipolar CML circuit 20, but contains MOS transistors M30, M31n, M31p, M32n, M32p, M33n and M33p in place of bipolar transistors Q30, Q31n, Q31p, Q32n, Q32p, Q33n and Q33p. 
The current source 14 of the MOS CML circuit 30 comprises the transistor M30 and the bias supply Vbias.
It follows from the above description that the voltage differential between the power supply terminals Vcc and Vee is distributed over five circuit elements in series in the case of the bipolar CML circuit 20, or four circuit elements in series in the case of the MOS CML circuit 30.
The voltage differential between the power supply terminals Vcc and Vee is determined by the technology (e.g. approximately 1.8 Volts for 0.18 micron CMOS technology) and therefore is inherently limited, because a smaller geometry technology, while yielding faster and more densely packed circuits, also implies a lower breakdown voltage for the devices.
As a result, a lower supply voltage has to be used for the smaller geometry circuits, which has several disadvantages: a lower drive voltage reduces the speed; and the distribution of the supply voltage across several logic stages and the bias stage leaves even less voltage available for each stage, thus further reducing the speed, and making the circuitry unsuitable for many higher speed applications.
Several techniques have been proposed in the industry to ameliorate this problem, for example, by eliminating the tail current source for biasing the circuit and replacing it by active biased loads in place of resistor loads, see, e.g. papers xe2x80x9cFully integrated 5.35-GHz CMOS VCOs and prescalersxe2x80x9d by Chih-Ming Hung et al., IEEE Transactions on Microwave Theory and Techniques, vol. 49, no. 1, January 2001, p. 17, and xe2x80x9cA fully integrated 1.5-V 5.5-GHz CMOS phase-locked loopxe2x80x9d by Chih-Ming Hung et al., IEEE Journal of Solid-State Circuits, vol. 37, no. 4, April 2002, p. 521.
Additionally, it has been proposed to further enhance the bandwidth of existing high-speed circuits by using optimized on-chip inductors to extend the frequency range of the circuits to higher speeds. Several of such enhancements have been described in the U.S. Pat. No. 6,340,899 to Green entitled xe2x80x9cCurrent-Controlled CMOS Circuits with Inductive Broadbandingxe2x80x9d issued Jan. 22, 2002, in the paper xe2x80x9cBandwidth Extension in CMOS with optimized on-chip inductorsxe2x80x9d by Sunderarajan S. Mohan et al., IEEE Journal of Solid-State Circuits, vol. 35, no. 3, March 2000, p. 346, and in another paper xe2x80x9cA CMOS interface circuit for detection of 1.2 Gb/s RZ dataxe2x80x9d by Jafar Savoj et al., 1999 IEEE International Solid-State Circuits Conference.
Unfortunately, the prior art techniques, while providing partial solutions to the above-mentioned problems, are inherently limited to high-speed applications operating at speeds of around 5 GHz or somewhat above and may not be always suitable for higher and substantially higher speed applications.
Accordingly, there is a need in the industry for further development of improved and flexible logic circuits, which would be suitable for high-speed applications.
Therefore it is an objective of the invention to provide high-speed logic circuits, which avoid the above-mentioned problems.
According to one aspect of the invention there is provided an electronic circuit arrangement, comprising:
a logic circuit having a differential input and a self-biasing clock buffer having a differential output, the self-biasing clock buffer comprising a driver circuit and a biasing circuit;
the driver circuit determining its operating point via negative feedback through the biasing circuit;
the differential output of the self-biasing clock buffer supplying a differential signal to the differential input of the logic circuit, the differential signal depending on the operating point of the driver circuit; and
the operating point of the logic circuit being set by the differential signal.
The operating point of the logic circuit is set through the common mode bias of the differential signal, the self-biasing clock buffer has an input, which is AC-coupled, and the differential signal is DC-coupled between the differential output of the self-biasing clock buffer and the differential input of the logic circuit.
The biasing circuit comprises a first and second of low-pass filters, and the self-biasing clock buffer comprises a first and second amplifier, each amplifier having an AC-coupled input, a biasing point and an output, the first and second low-pass filters providing the negative feedback from the output to the biasing point of the corresponding amplifiers.
Beneficially, each amplifier comprises a MOS transistor, the biasing point of the amplifier being the gate of the transistor and the output being the drain of the transistor. Advantageously, the logic circuit and the self-biasing clock buffer are made on the same substrate and by the same technology. The operating point of the logic circuit may be further determined by relative sizes of MOS transistors between the logic circuit and the self-biasing circuit as required.
Additionally, for extending the frequency response of the circuit arrangement and the bandwidth of the logic circuit, one or both of the driver circuit and the logic circuit may comprise a tuned means for modifying the frequency response of the respective circuit, the tuned means comprising one of the following:
an inductive means adjusted to increase (he bandwidth of the respective circuit; and
a resonant means adjusted to resonate at substantially the frequency of the differential signal.
In the embodiments of the invention, the logic circuit is one or more of the following:
a multiplexer circuit;
a latch circuit;
a data buffer; and
a flip-flop comprising two latch circuits.
The multiplexer circuit has a differential select input and a first and second differential data input, and the differential signal is applied to the differential select input.
Advantageously, the logic circuit described above is a flexible logic circuit comprising:
an upper group of two transistor pairs, and a lower group of two transistor pairs;
each group of transistors pairs comprising a left pair of transistors and a right pair of transistors;
the sources of the transistors in the lower group being connected to a first power supply terminal;
the drains of the transistors in the lower group are connected to the sources of the corresponding transistors in the upper group;
the drains of the transistors of the left pair in the upper group are connected to a first lead of a load element whose second lead is connected to a second power supply terminal;
the drains of the transistors of the right pair in the upper group are connected to a first lead of another load element whose second lead is connected to the second power supply terminal;
the drains of the transistors of the left and right pairs in the upper group providing the differential output of the flexible logic circuit;
the gates of the transistors are capable of being connected to differential outputs of any of the following according to a required topology:
of the clock buffer;
of said flexible logic circuit;
of another logic circuit; and
the topology determining a required logic function of the flexible logic circuit.
Conveniently, the load elements are resistors. Additionally, one or both of the driver circuit and the flexible logic circuit comprises a tuned means for modifying the frequency response of the respective circuit, the tuned means comprising one of the following:
an inductive means adjusted to increase the bandwidth of the respective circuit; and
a resonant means adjusted to resonate at substantially the frequency of the differential signal.
In the embodiments of the invention the topology of the flexible logic circuit is chosen o that the required logic function is that of a multiplexer or of a latch.
If required, the logic circuit may comprise more than one logic circuit driven by the elf-biasing clock buffer, wherein said more than one logic circuits are optionally connected through one or more data buffers. Conveniently, said more than one logic circuits are interconnected so as to form one or more of the following:
a serializer;
a deserializer;
a clock divider;
a phase detector.
The circuit arrangement of the embodiments of the invention may be manufactured on the same substrate in combination with other circuitry, e.g. the circuit arrangement being implemented as MOS circuitry, and the other circuitry being implemented as CMOS circuitry. The MOS circuitry may provide a bridge between serial high speed input and output (IO) ports, and the CMOS circuitry may comprise a communications processor.
According to another aspect of the invention there is provided a circuit arrangement comprising circuitry of a first technology and another circuitry of a second technology, the circuitry of the first technology including:
a logic circuit having a differential input and a self-biasing clock buffer having a differential output, the self-biasing clock buffer comprising a driver circuit and a biasing circuit;
the driver circuit determining its operating point via negative feedback through the biasing circuit;
the differential output of the self-biasing clock buffer supplying a differential signal to
the differential input of the logic circuit, the differential signal depending on the operating point of the driver circuit; and
the operating point of the logic circuit being set by the differential signal.
Beneficially, the first technology is MOS, and the second technology is CMOS. The circuit arrangement described above may be part of a semiconductor device, and if required, it may be manufactured in an electronic package.
The embodiments of the invention, including a novel high-speed circuit family described above and termed QTL (Quake Transistor Logic), provides the following advantages.
A novel clock buffer design provides a differential clock signal with a common mode DC bias eliminating the need for tail current sources in the logic circuits, thus improving performance.
Further advantages in lower power consumption and higher maximum operating speed are provided by differential tuned clock buffers and corresponding design of the logic circuits.
A flexible logic circuit topology provides the ability to optimize each circuit for specific needs, such as voltage swing, power, and propagation time.
The low power requirement and the very high operating speed enable the circuits of the embodiments of the invention to be combined with other, lower speed circuits on a single substrate, e.g. silicon substrate, by using a common manufacturing technology, e.g. CMOS.